Datenblatt-Suchmaschine für elektronische Bauteile |
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AD809BR-REEL7 Datenblatt(PDF) 1 Page - Analog Devices |
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AD809BR-REEL7 Datenblatt(HTML) 1 Page - Analog Devices |
1 / 8 page REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 155.52 MHz Frequency Synthesizer AD809 FEATURES Frequency Synthesis to 155.52 MHz 19.44 MHz or 9.72 MHz Input Reference Signal Select Mux Single Supply Operation: +5 V or –5.2 V Output Jitter: 2.0 Degrees RMS Low Power: 90 mW 10 KH ECL/PECL Compatible Output 10 KH ECL/PECL/TTL/CMOS Compatible Input Package: 16-Pin Narrow 150 Mil SOIC One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 155.52 Mbps ports. The AD809 can be applied to create the trans- mit bit clock for one or more ports. An input signal multiplexer supports loop-timed applications where a 155.52 MHz transmit bit clock is recovered from the 155.52 Mbps received data. The low jitter VCO, low power and wide operating temperature range make the device suitable for generating a 155.52 MHz bit clock for SONET/SDH/Fiber in the Loop systems. The device has a low cost, on-chip VCO that locks to either 8 × or 16× the frequency at the 19.44 MHz or 9.72 MHz input. No external components are needed for frequency synthesis; how- ever, the user can adjust loop dynamics through selection of a damping factor capacitor whose value determines loop damping. The AD809 design guarantees that the clock output frequency will drift low (by roughly 20%) in the absence of a signal at the input. The AD809 consumes 90 mW and operates from a single power supply at either +5 V or –5.2 V. PRODUCT DESCRIPTION The AD809 provides a 155.52 MHz ECL/PECL output clock from either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL refer- ence frequency. The AD809 functionality supports a distributed timing architecture, allowing a backplane or PCB 19.44 MHz or 9.72 MHz timing reference signal to be distributed to multiple FUNCTIONAL BLOCK DIAGRAM AUTO SELECT PFD LOOP FILTER VCO AUTO SELECT DIVIDE BY 8/16 BW ADJUST MUX CLKOUTN (155MHz PECL OUTPUT) CLKIN TTL/CMOSIN (155MHz) MUX CF1 CF2 AD809 15 1 2 10 12 13 7 8 5 4 CLKOUT (19.44MHz OR 9.72MHz)CLKINN PECLIN PECLINN |
Ähnliche Teilenummer - AD809BR-REEL7 |
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Ähnliche Beschreibung - AD809BR-REEL7 |
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