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AD8314ARM-REEL Datenblatt(PDF) 9 Page - Analog Devices |
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AD8314ARM-REEL Datenblatt(HTML) 9 Page - Analog Devices |
9 / 16 page AD8314 –9– REV. 0 frequencies, due to the declining gain of the amplifier stages and other effects in the detector cells. For the AD8314, the slope at low frequencies is nominally 21.3 mV/dB, falling almost linearly with frequency to about 19.2 mV/dB at 2.5 GHz. These values are sensibly independent of temperature (see Figure 7) and almost totally unaffected by the supply voltage from 2.7 V to 5.5 V (Figure 8). Inverted Output The second provision is the inclusion of an inverting amplifier to the output, for use in controller applications. Most power amplifiers require a gain-control bias that must decrease from a large positive value toward ground level as the power output is required to decrease. This control voltage, which appears at the pin V_DN, is not only of the opposite polarity to V_UP, but also needs to have an offset added in order to determine its most posi- tive value when the power level (assumed to be monitored through a directional coupler at the output of the PA) is minimal. The starting value of V_DN is nominally 2.25 V, and it falls on a slope of twice that of V_UP, in other words, –43 mV/dB. Figure 26 shows how this is achieved: the reference voltage that determines the maximum output is derived from the on- chip voltage reference, and is substantially independent of the supply voltage or temperature. However, the full output cannot be attained for supply voltages under 3.3 V; Figure 19 shows this dependency. The relationship between V_UP and V_DN is shown in Figure 27. V–I BAND-GAP REFERENCE +2 VSET FLTR I–V 1.125V VDN = 2.25V – 2.0 V_UP CURRENTS FROM DETECTORS AD8314 V_UP V_DN Figure 26. Output Interfaces INPUT AMPLITUDE – dBV 0 –60 2.5 2.0 1.5 1.0 0.5 OUTPUT FOR PA CONTROL –50 –40 –30 –20 –10 0 OUTPUT FOR MEASUREMENT V_UP V_DN Figure 27. Showing V_UP and V_DN Relationship APPLICATIONS Basic Connections Figure 28 shows connections for the basic measurement mode. A supply voltage of 2.7 V to 5.5 V is required. The supply to the VPOS pin should be decoupled with a low inductance 0.1 µF surface mount ceramic capacitor. A series resistor of about 10 Ω may be added; this resistor will slightly reduce the supply voltage to the AD8314 (maximum current into the VPOS pin is approxi- mately 9 mA when V_DN is delivering 5 mA). Its use should be avoided in applications where the power supply voltage is very low (i.e., 2.7 V). A series inductor will provide similar power supply filtering with minimal drop in supply voltage. 1 2 3 4 ENBL RFIN AD8314 8 7 6 5 VSET FLTR V DN VPOS COMM V UP 0.1 F OPTIONAL (SEE TEXT) OPTIONAL (SEE TEXT) VS VDN VUP CF VS 52.3 INPUT Figure 28. Basic Connections for Operation in Measurement Mode The ENBL pin is here connected to VPOS. The AD8313 may be disabled by pulling this pin to ground when the chip current is reduced to about 20 µA from its normal value of 4.5 mA. The logic threshold is around +VS/2 and the enable function occurs in about 1.5 µs. Note, however, further settling time is generally needed at low input levels. The AD8314 has an internal input coupling capacitor. This eliminates the need for external ac-coupling. A broadband input match is achieved in this example by connecting a 52.3 Ω resis- tor between RFIN and ground. This resistance combines with the internal input impedance of approximately 3 k Ω to give an overall broadband input resistance of 50 Ω. Several other coupling methods are possible; these are described in the Input Coupling section. The measurement mode is selected by connecting VSET to V_UP, which establishes a feedback path and sets the logarithmic slope to its nominal value. The peak voltage range of the measurement extends from –58 dBV to –13 dBV at 0.9 GHz, and only slightly less at higher frequencies up to 2.5 GHz. Thus, using the 50 Ω termination, the equivalent power range is –45 dBm to 0 dBm. At a slope of 21.5 mV/dB, this would amount to an output span of 967 mV. Figure 29 shows the transfer function for V_UP at a supply voltage of 3 V, and input frequency of 0.9 GHz. V_DN, which will generally not be used when the AD8314 is used in the measurement mode, is essentially an inverted version of V_UP. The voltage on V_UP and V_DN are related by the equation. VDN = 2.25 V – 2 VUP While V_DN can deliver up to 6 mA, the load resistance on V_UP should not be lower than 10 k Ω in order that the full-scale output of 1 V can be generated with the limited available current of 200 µA max. Figure 29 shows the logarithmic conformance under the same conditions. |
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