REV. 0

AD9742

–5–

PIN CONFIGURATION

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

AD9742

NC = NO CONNECT

(MSB) DB11

DB10

DB7

DB6

DB5

DB4

DB3

DB2

DB1

(LSB) DB0

NC

NC

CLOCK

DVDD

DCOM

MODE

AVDD

RESERVED

IOUTA

IOUTB

ACOM

NC

FS ADJ

REFIO

REFLO

SLEEP

DB8

DB9

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1

DB11

Most Significant Data Bit (MSB)

2–11

DB10–DB1

Data Bits 10–1

12

DB0

Least Significant Data Bit (LSB)

13, 14

NC

No Internal Connection

15

SLEEP

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left

unterminated if not used.

16

REFLO

Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference.

17

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO

to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND).

Requires 0.1

mF capacitor to AGND when internal reference activated.

18

FS ADJ

Full-Scale Current Output Adjust

19

NC

No Internal Connection

20

ACOM

Analog Common

21

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

22

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

23

RESERVED

Reserved. Do Not Connect to Common or Supply.

24

AVDD

Analog Supply Voltage (3.3 V)

25

MODE

Selects Input Data Format. Connect to DGND for straight binary, DVDD for two’s complement.

26

DCOM

Digital Common

27

DVDD

Digital Supply Voltage (3.3 V)

28

CLOCK

Clock Input. Data latched on positive edge of clock.