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ADF4112 Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer ADF4112
Bauteilbeschribung  RF PLL Frequency Synthesizers
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REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
I
R
CP
SET
max
.
=
23 5
So, with RSET = 4.7 k
Ω, I
CPmax = 5 mA.
2
CP
Charge Pump Output. When enabled this provides
±ICP to the external loop filter, which in turn drives the
external VCO.
3
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
AGND
Analog Ground. This is the ground return path of the prescaler.
5RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 25.
6RFINA
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7AVDD
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resis-
tance of 100 k
Ω. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
DGND
Digital Ground.
10
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
11
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
14
MUXOUT
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
15
DVDD
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RSET
VP
ADF4110
ADF4111
ADF4112
ADF4113
CP
DVDD
CPGND
MUXOUT
AGND
LE
RFINB
DATA
RFINA
CLK
AVDD
CE
REFIN
DGND
CHIP SCALE PACKAGE
TOP VIEW
(Not to Scale)
CPGND
AGND
AGND
RFINB
RFINA
MUXOUT
LE
DATA
CLK
CE
ADF4110
ADF4111
ADF4112
ADF4113
1
2
3
4
5
15
14
13
12
11


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