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ADF4113 Datenblatt(PDF) 11 Page - Analog Devices

Teilenummer ADF4113
Bauteilbeschribung  RF PLL Frequency Synthesizers
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REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
–11–
PROGRAMMABLE
DELAY
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HI
HI
U1
ABP1
ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
VP
Figure 27. PFD Simplified Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 28 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 k
Ω nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
CONTROL
MUX
DVDD
MUXOUT
DGND
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 28. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
R Counter
0
1
N Counter (A and B)
1
0
Function Latch (Including Prescaler)
1
1
Initialization Latch


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