REV. A

ADM1028

–6–

FREQUENCY – Hz

2

1

1

0

1k

1M

10

100

10k

100k

10M

100M

1B

TPC 7. Temperature Error vs. Differential-Mode

Noise Frequency

TEMPERATURE – C

2.3

1.7

–40

1.5

1.6

1.8

1.9

2.0

2.1

2.2

–20

0

20

40

60

80

100

130

–10

–30

10

30

50

70

90

120

TPC 8. Standby Supply Current vs. Temperature

FUNCTIONAL DESCRIPTION

The ADM1028 is a low-cost temperature monitor and fan con-

troller for microprocessor-based systems. The temperature of

a remote sensor diode may be measured, allowing monitoring

of processor temperature in a single-processor system. An on-

chip temperature sensor allows monitoring of system ambient

temperature.

Measured values can be read out via the serial System Manage-

ment Bus, and values for limit comparisons can be programmed

in over the same serial bus.

The ADM1028 also contains a DAC for fan speed control. An

automatic hardware temperature trip point is provided for fault

tolerant fan control and the fan will be driven to full speed if this

is exceeded. Two interrupt outputs are provided, which will be

asserted if the software or hardware limits are exceeded.

Finally, the chip has remote reset and shutdown capabilities.

INTERNAL REGISTERS OF THE ADM1028

A brief description of the ADM1028’s principal internal registers

is given below. More detailed information on the function of

each register is given in Tables III to IX.

Configuration Register: Provides control and configuration.

Address Pointer Register: This register contains the address

that selects one of the other internal registers. When writing to

the ADM1028, the first byte of data is always a register address,

which is written to the Address Pointer Register.

Interrupt (

INT) Status Register: This register provides sta-

tus of each Interrupt event.

Interrupt (

INT) Mask Register: Allows masking of individual

interrupt sources.

Value and Limit Registers: The results of temperature mea-

surements are stored in these registers, along with their limit values.

Analog Output Register: The code controlling the analog

output DAC is stored in this register.

Alert Status Register: Indicates the status of the

THERM

signal and GPI pin.

Remote Function Register: This register allows control of the

R_RST and R_OFF outputs.

Fan Speed Ramp Register: This register allows enabling/

disabling of DAC ramp, as well as providing control of fan

speed ramp rate.

SERIAL BUS INTERFACE

Control of the ADM1028 is carried out via the serial bus. The

ADM1028 is connected to this bus as a slave device, under the

control of a master device, e.g. the 810 chipset.

The ADM1028 has a 7-bit serial bus address. When the device

powers up, it will do so with a default serial bus address. The

SMBus address for the ADM1028 is 0101110 binary.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line SCL remains high.

This indicates that an address/data stream will follow. All

slave peripherals connected to the serial bus respond to the

START condition, and shift in the next eight bits, consisting

of a 7-bit address (MSB first) plus an R/

W bit, which deter-

mines the direction of the data transfer, i.e., whether data

will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the Acknowl-

edge Bit. All other devices on the bus now remain idle while

the selected device waits for data to be read from or written

to it. If the R/

W bit is a 0, the master will write to the slave

device. If the R/

W bit is a 1, the master will read from the

slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an Acknowledge Bit

from the slave device. Transitions on the data line must occur

during the low period of the clock signal and remain stable

during the high period, as a low-to-high transition when the

clock is high may be interpreted as a STOP signal. The num-

ber of data bytes that can be transmitted over the serial bus

in a single READ or WRITE operation is limited only by

what the master and slave devices can handle.

3. When all data bytes have been read or written, stop condi-

tions are established. In WRITE mode, the master will pull

the data line high during the tenth clock pulse to assert a