ADM8696/ADM8697

REV. 0

–10–

TYPICAL APPLICATIONS

ADM8696

Figure 18 shows the ADM8696 in a typical power monitoring,

power for the CMOS RAM.

Power Fail

RESET

1.3 V.

above 1.3 V. This allows for a power-on reset and prevents re-

peated toggling of

reset threshold.

Watchdog Timer

The Watchdog Timer Input (WDI) monitors an I/O line from

the

µP system. This line must be toggled once every 1.6 s to

verify correct software execution. Failure to toggle the line indi-

cates that the

µP system is not correctly executing its program

and may be tied up in an endless loop. If this happens, a reset

pulse is generated to initialize the processor.

If the watchdog timer is not needed the WDI input should be

left floating.

Power Fail Detector

The Power Fail Input, PFI, monitors the input power supply via

a resistive divider network R1 and R2. This input is intended as

an early warning power fail input. The voltage on the PFI input

is compared with a precision 1.3 V internal reference. If the in-

put voltage drops below 1.3 V, a power fail output (PFO) signal

is generated. This warns of an impending power failure and may

be used to interrupt the processor so that the system may be

shut down in an orderly fashion. The resistors in the sensing

network are ratioed to give the desired power fail threshold volt-

RESET threshold so there is sufficient time available to com-

plete the shutdown procedure before the processor is RESET

and power is lost.

ADM8696

R2

R1

PFO

+5V

CMOS RAM

POWER

I/O LINE

µP NMI

µP SYSTEM

µP POWER

WDI

GND

PFI

BATTERY

RESET

µP RESET

+

R4

R3

RESET

Figure 18a. ADM8696 Typical Application Circuit A

Figure 18b shows a similar application for the ADM8696 but in

this case the PFI input monitors the unregulated input to the

7805 voltage regulator. This gives an earlier warning of an im-

pending power failure. It is useful with processors operating at

low speeds or where there are a significant number of house-

keeping tasks to be completed before the power is lost.

ADM8696

R2

R1

PFO

INPUT

POWER

GND

PFI

0.1

µF

3V

BATTERY

RESET

OSC IN

OSC SEL

SYSTEM STATUS

INDICATORS

LOW LINE

CMOS RAM

I/O LINE

NMI

RESET

A0–A15

µP

BATT

ON

NC

WDI

µP

POWER

RESET

R4

R3

7805

WDO

0.1

µF

Figure 18b. ADM8696 Typical Application Circuit B

This application also shows an optional external transistor that

low, providing 25 mA of base drive for the external PNP transis-

tor. The maximum current available is dependent on the power

rating of the external transistor.

RAM Write Protection

The ADM8697

CMOS RAM.

goes high, independent of the logic level at

the microprocessor from writing erroneous data into RAM dur-

ing power-up, power-down, brownouts and momentary power

interruptions.