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ADM8697ARU Datenblatt(PDF) 5 Page - Analog Devices |
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ADM8697ARU Datenblatt(HTML) 5 Page - Analog Devices |
5 / 12 page ADM8696/ADM8697 REV. 0 –5– Low Line RESET OUTPUT RESET is an active low output that provides a RESET signal to the microprocessor whenever the Low Line Input (LLIN) is be- low 1.3 V. The LLIN input is normally used to monitor the power supply voltage. An internal timer holds RESET low for 50 ms after the voltage on LLIN rises above 1.3 V. This is in- tended as a power-on RESET signal for the processor. It allows time for the power supply and microprocessor to stabilize. On power-down, the RESET output remains low, with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. The LLIN comparator has approximately 12 mV of hysteresis for enhanced noise immunity. In addition to RESET, an active high RESET output is also available. This is the complement of RESET and is useful for processors requiring an active high RESET. t 1 t 1 = RESET TIME V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 V2 V2 V1 V1 t1 LL IN LOW LINE RESET Figure 2. Power-Fail Reset Timing Watchdog Timer RESET The watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a RESET pulse is generated. The ADM8696/ADM8697 may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. If the “short” period is selected, some systems may be unable to service the watchdog timer im- mediately after a reset, so a “long” timeout is automatically ini- tiated directly after a reset is issued. The watchdog timer is restarted at the end of Reset, whether the Reset was caused by lack of activity on WDI or by LLIN falling below the reset threshold. The normal (short) timeout period becomes effective following the first transition of WDI after RESET has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be is- sued after each timeout period (1.6 s). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI) or by connecting it to midsupply. CIRCUIT INFORMATION Battery Switchover Section (ADM8696) The battery switchover circuit is designed to switch over to battery backup in the event of a power failure. When LLIN is below the reset threshold and VCC is below VBATT, then VBATT is switched to VOUT. During normal operation, with VCC higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typical on resistance of 0.7 Ω and can supply up to 100 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instanta- neous currents of greater than 100 mA. If this is the case, then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capaci- tance value of 0.1 µF or greater may be used. If the continuous output current requirement at VOUT exceeds 100 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can directly drive the base of the external transistor. A 7 Ω MOSFET switch connects the V BATT input to VOUT dur- ing battery backup. This MOSFET has very low input-to-out- put differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typi- cally 0.4 µA. The ADM8696 operates with battery voltages from 2.0 V to VCC–0.3 V). High value capacitors, either standard electrolytic or the farad-size double layer capacitors, can also be used for short-term memory backup. A small charging current of typi- cally 10 nA (0.1 µA max) flows out of the V BATT terminal. This current is useful for maintaining rechargeable batteries in a fully charged condition. This extends the life of the backup battery by compensating for its self-discharge current. Also note that this current poses no problem when lithium batteries are used for backup since the maximum charging current (0.1 µA) is safe for even the smallest lithium cells. If the battery switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. V BATT V CC BATT ON (ADM8691, ADM8693, ADM8695, ADM8696) V OUT 700 mV 100 mV GATE DRIVE INTERNAL SHUTDOWN SIGNAL WHEN V BATT > (VCC + 0.7V) Figure 1. Battery Switchover Schematic |
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