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ADSP-2191MBST-140 Datenblatt(PDF) 9 Page - Analog Devices |
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ADSP-2191MBST-140 Datenblatt(HTML) 9 Page - Analog Devices |
9 / 52 page –9– REV. 0 ADSP-2191M each byte access that does not start a read or complete a write. Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully. DSP Serial Ports (SPORTs) The ADSP-2191M incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features: • Bidirectional operation—each SPORT has independent transmit and receive pins. • Double-buffered transmit and receive ports—each port has a data register for transferring data words to and from memory and shift registers for shifting data in and out of the data registers. • Clocking—each transmit and receive port can either use an external serial clock ( 40 MHz) or generate its own, in frequencies ranging from 19 Hz to 40 MHz. • Word length—each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format. • Framing—each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. • Companding in hardware—each SPORT can perform A-law or µ-law companding according to ITU recommen- dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead—each SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. Either the DSP’s core or a Host processor can link or chain sequences of DMA transfers between a SPORT and memory. The chained DMA can be dynamically allocated and updated through the DMA descriptors (DMA transfer parameters) that set up the chain. • Interrupts—each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. • Multichannel capability—each SPORT supports the H.100 standard. Serial Peripheral Interface (SPI) Ports The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input-Slave Output, MISOx) and a clock pin (Serial Clock, SCKx). Two SPI chip select input pins ( SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins (SPIxSEL7–1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports provide a full duplex, synchronous serial inter- face, which supports both master and slave modes and multimaster environments. Each SPI port’s baud rate and clock phase/polarities are program- mable (see equation below for SPI clock rate calculation), and each has an integrated DMA controller, configurable to support both transmit and receive data streams. The SPI’s DMA control- ler can only service unidirectional accesses at any given time. During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines. UART Port The UART port provides a simplified UART interface to another peripheral or Host. It performs full duplex, asynchronous transfers of serial data. Options for the UART include support for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART port supports two modes of operation: • Programmed I/O The DSP’s core sends or receives data by writing or reading I/O-mapped THR or RBR registers, respectively. The data is double-buffered on both transmit and receive. • DMA (direct memory access) The DMA controller transfers both transmit and receive data. This reduces the number and frequency of inter- rupts required to transfer data to and from memory. The UART has two dedicated DMA channels. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. The UART’s baud rate (see following equation for UART clock rate calculation), serial data format, error code generation and status, and interrupts are programmable: • Supported bit rates range from 9.5 bits to 5M bits per second (80 MHz peripheral clock). • Supported data formats are 7- to 12-bit frames. • Transmit and receive status can be configured to generate maskable interrupts to the DSP’s core. The timers can be used to provide a hardware-assisted autobaud detection mechanism for the UART interface. Where D is the programmable divisor = 1 to 65536. SPI Clock Rate HCLK 2 SPIBAUD × --------------------------------------- = UART Clock Rate HCLK 16 D × ------------------ = |
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Ähnliche Beschreibung - ADSP-2191MBST-140 |
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