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ADV7197 Datenblatt(PDF) 11 Page - Analog Devices |
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ADV7197 Datenblatt(HTML) 11 Page - Analog Devices |
11 / 20 page REV. 0 ADV7197 –11– A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral. The ADV7197 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/ W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subad- dress register on a one-by-one basis without having to update all the registers. Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one Start condition, one Stop condition or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7197 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode, the user exceeds the highest subaddress, the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no- acknowledge condition is where the SDA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7197 and the part will return to the idle condition. DATA A(S) S SLAVE ADDR A(S) SUB ADDR A(S) LSB = 0 LSB = 1 DATA A(S) P S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) A(M) DATA P WRITE SEQUENCE READ SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO-ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO-ACKNOWLEDGE BY MASTER Figure 10. Write and Read Sequence SR4 SR3 SR2 SR1 SR0 SR7 SR6 SR5 ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR0 00h 0 0 0 0000 MODE REGISTER 0 01h 0 0 0 0001 MODE REGISTER 1 02h 0 0 0 0010 MODE REGISTER 2 03h 0 0 0 0011 MODE REGISTER 3 04h 0 0 0 0100 MODE REGISTER 4 05h 0 0 0 0101 MODE REGISTER 5 06h 0 0 0 0110 COLOR Y 07h 0 0 0 0111 COLOR CR 08h 0 0 0 1000 COLOR CB ADV7197 SUBADDRESS REGISTER ZERO SHOULD BE WRITTEN HERE SR7 Figure 11. Subaddress Registers 1–7 8 9 89 8 9 P S START ADDR R/ W ACK SUBADDRESS ACK DATA ACK STOP SDATA SCLOCK 1–71–7 Figure 9. Bus Data Transfer Figure 9 illustrates an example of data transfer for a read sequence and the Start and Stop conditions. Figure 10 shows bus write and read sequences. REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7197 except the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register is accessed by the next read or write operation. All communications with the part through the bus begin with an access to the Subaddress Register. A read/write operation is performed from/to the target address which then increments to the next address until a Stop command on the bus is performed. REGISTER PROGRAMMING The following section describes the functionality of each regis- ter. All registers can be read from as well as written to unless otherwise stated. Subaddress Register (SR7–SR0) The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. Figure 11 shows the various operations under the control of the Subaddress Register. “0” should always be written to SR7. Register Select (SR6–SR0) These bits are set up to point to the required starting address. |
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