Datenblatt-Suchmaschine für elektronische Bauteile |
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DAC10GS Datenblatt(PDF) 8 Page - Analog Devices |
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DAC10GS Datenblatt(HTML) 8 Page - Analog Devices |
8 / 10 page DAC10 –8– REV. D APPLICATIONS DAC10 OPTIONAL RESISTOR FOR OFFSET INPUTS RREF RL RL 2 4 17 16 RP RIN +VREF REQ = 800 NO CAP 0V TYPICAL VALUES: RIN = 1k +VIN = 2V 1 RIN 1 RP 1 RREF + REQ = + 1 Figure 18. Pulsed Reference Operation Reference Amplifier Setup The DAC10 is a multiplying D/A converter in which the output current is the product of a digital number and the input refer- ence current. The reference current may be fixed or may vary from nearly zero to 2 mA. The full-scale output current is a linear function of the reference current and is given by: I FR = 1023 1024 × 2 × I REF where IREF equals current flowing into Pin 16. In positive reference applications, an external positive reference voltage forces current through R16 into the VREF (+) terminal (Pin 16) of the reference amplifier. Alternatively, a negative reference may be applied to VREF (–) at Pin 17; reference current flows from ground through R16 into V(+) as in the positive reference case. This negative reference connection has the ad- vantage of a very high impedance presented at Pin 17. R17 (nominally equal to R16) is used to cancel bias current errors; R17 may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting VREF or Pin 17. The negative common-mode range of the reference amplifier is given by: VCM– = V– plus (IREF × 2 kΩ) plus 2 V. The positive common-mode range is V+ less 1.8 V. When a dc reference is used, a reference bypass capacitor is recommended. A 5 V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R16 should be split into two resistors with the junction bypassed to ground with a 0.1 µF capacitor. For most applications, the tight relationship between IREF and IFS will eliminate the need for trimming IREF. If required, full- scale trimming may be accomplished by adjusting the value of R16, or by using a potentiometer for R16. An improved method of full-scale trimming that eliminates potentiometer TC effect is shown in the Recommended Full-Scale Adjustment circuit. The reference amplifier must be compensated by using a capaci- tor from Pin 18 to V–. For fixed reference operation, a 0.01 µF capacitor is recommended. For variable reference applications, see section entitled Reference Amplifier Compensation for Mul- tiplying Applications. Multiplying Operation The DAC10 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 4 mA to 4 µA. Monotonic operation is maintained over a typical range of IREF from 100 µA to 2 mA. Reference Amplifier Compensation for Multiplying Applications AC reference applications will require the reference amplifier to be compensated using a capacitor from Pin 18 to V–. The value of this capacitor depends on the impedance presented to Pin 16 for R16 values of 1.0 k Ω, 2.5 kΩ and 5.0 kΩ, minimum values of CC are 15 pF, 37 pF and 75 pF. Larger values of R16 require proportionately increased values of CC for proper phase margin. For fastest response to a pulse, low values of R16 enabling small CC values should be used. If Pin 16 is driven by a high imped- ance such as a transistor current source, none of the above val- ues will suffice and the amplifier must be heavily compensated, which will decrease overall bandwidth and slew rate. For R16 = 1k Ω and C C = 15 pF, the reference amplifier slews at 4 mA/ µs enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) occurs in 120 ns when the equivalent impedance at Pin 16 is 200 Ω and C C = 0. This yields a reference slew rate of 16 mA/ µs, which is relatively independent of R IN and VIN values. LOGIC INPUTS The DAC10 design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made pos- sible by the large input swing capability, 2 µA logic input current and completely adjustable logic threshold voltage. For V– = –15 V, the logic inputs may swing between –5 and +18 V. This enables direct interface with +15 V CMOS logic, even when the DAC10 is powered from a +5 V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V– plus (lREF × 2k Ω) plus 3 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control Pin (Pin 1, VLC). The appropriate graph shows the relationship between VLC and VTH over the temperature range, with VTH nominally 1.4 V above VLC. For TTL interface, simply ground Pin 1. When interfacing ECL, an IREF = 1 mA is recom- mended. For interfacing other logic families, see Figure 17. For general setup of the logic control circuit, it should be noted that Pin 1 will sink 1.1 mA typical; external circuitry should be de- signed to accommodate this current. Fastest settling times are obtained when Pin 1 sees a low imped- ance. If Pin 1 is connected to a 1 k Ω divider, for example, it should be bypassed to ground by a 0.01 µF capacitor. |
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Ähnliche Beschreibung - DAC10GS |
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