Datenblatt-Suchmaschine für elektronische Bauteile |
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TPD5S116 Datenblatt(PDF) 2 Page - Texas Instruments |
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TPD5S116 Datenblatt(HTML) 2 Page - Texas Instruments |
2 / 28 page ERC 26kΩ ERC 5V_CON 1.75kΩ ERC 5V_CON 1.75kΩ SCL_SYS SCL_CON SDA_SYS SDA_CON CEC_SYS CEC_CON 3.3V (Internal) 2 Level Shifter & LDO Control EN 100kΩ 5V VCCA HPD_SYS HPD_CON 1. EN pin enables the load switch and HPD buffer 2. When EN = H & HPD_CON = H, the 3.3V LDO for CEC pin, DDC and CEC level shifting buffers are enabled VCCA 5kΩ VCCA 5kΩ VCCA 5kΩ 470kΩ 10MΩ UTI_CON 100kΩ LDO 55mA Load Switch 5V_CON 5V_SYS TPD5S116 SLVSBP3 – DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C YFF Tape and reel TPD5S116YFFR RE116 (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT SCHEMATIC DIAGRAM Figure 1. Circuit Schematics 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPD5S116 |
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