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USS-820D Datenblatt(PDF) 8 Page - Agere Systems

Teilenummer USS-820D
Bauteilbeschribung  USS-820D USB Device Controller
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8
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Pin Information (continued)
Table 2. Pin Descriptions
* Active-low signals within this document are indicated by an N following the symbol names.
† Pins marked as NC must have no external connections, except where noted.
44-Pin MQFP
(USS-820D)
48-Pin TQFP
(USS-820TD)
Symbol*
Type
Name/Description
12
VDDA
P
3.3 V Power Supply for Analog PLL.
2
3
XTAL1
I
Crystal/Clock Input. If the internal oscillator is used, this is
the crystal input. If an external oscillator is used, this is the
clock input.
3
4
XTAL2
O
Crystal/Clock Output. If the internal oscillator is used, this
is the crystal output. If an external oscillator is used, this
output should be left unconnected.
45
VDDT
P
3.3 V Power Supply for USB Transceiver.
5
6
DMNS
I/O
USB Differential Data Bus Minus.
6
7
DPLS
I/O
USB Differential Data Bus Plus.
78
VSST
P
Device Ground for USB Transceiver.
12, 11, 10, 9,
8
13, 12, 11,
10, 9
A[4:0]
I
Address Bus. This is the address bus for the controller to
access the register set.
13
14
VSSX
P
Device Ground. For compatibility with USS-820 revision B,
this pin can be connected to a controller address bit, as
long as it is guaranteed to be equal to 0 during register
accesses and meets all address pin timing requirements.
14, 20, 21,
22, 23, 24,
34, 40
15, 22, 23,
24, 25, 26,
37, 43
VSS0, VSS1,
VSS2, VSSX
P
Device Ground.
15
16
DSA
O
Data Set Available. Indicates one or more receive data
sets are valid, or one or more transmit data sets are empty
(available). For compatibility with USS-820 revision B, this
output is 3-stated if MCSR.BDFEAT = 0.
18
19
USBR
O
USB Reset Detected. Indicates a USB reset event has
been detected on USB. This pin will remain asserted until
the SSR.RESET register bit is cleared by firmware. For
compatibility with USS-820 revision B, this output is 3-
stated if MCSR.BDFEAT = 0.
16
1, 17, 20, 21,
27
NC
No Connect.
17, 44
18, 47
VDD0, VDD1
P
3.3 V Power Supply.
19
48
DPPU
O
DPLS Pull-Up. Can be used to supply power to the DPLS
1.5 k
Ω pull-up resistor to allow firmware to simulate a
device physical disconnect. This pin is directly controlled by
the DPEN register bit.
25
28
RWUPN
I
Remote Wake-Up (Active-Low). Device is initiating a
remote wake-up from a suspend condition. This input is
ignored if SCR register bit RWUPE = 0.
26
29
SUSPN
O
Suspend (Active-Low). USB suspend has been detected;
chip has entered suspend (low power) mode. This pin is
deasserted when a wake-up event is detected.


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