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74ABT373CMSA Datenblatt(PDF) 5 Page - Fairchild Semiconductor

Teilenummer 74ABT373CMSA
Bauteilbeschribung  Octal Transparent Latch with 3-STATE Outputs
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74ABT373CMSA Datenblatt(HTML) 5 Page - Fairchild Semiconductor

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Extended AC Electrical Characteristics
(SOIC Package)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500
:, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). This specification is guaranteed but not tested.
Note 15: Propagation delay variation is for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but
not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Note 17: COUT is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
TA 40qC to 85qCTA 40qC to 85qCTA 40qC to 85qC
Units
VCC 4.5V to 5.5V
VCC 4.5V to 5.5V
VCC 4.5V to 5.5V
CL 50 pF
CL 250 pF
CL 250 pF
8 Outputs Switching
8 Outputs Switching
(Note 8)
(Note 9)
(Note 10)
MinMax
MinMax
MinMax
tPLH
Propagation Delay
1.5
5.2
2.0
6.8
2.0
9.0
ns
tPHL
Dn to On
1.5
5.2
2.0
6.8
2.0
9.0
tPLH
Propagation Delay
1.5
5.5
2.0
7.5
2.0
9.5
ns
tPHL
LE to On
1.5
5.5
2.0
7.5
2.0
9.5
tPZH
Output Enable Time
1.5
6.2
2.0
8.0
2.0
10.5
ns
tPZL
1.5
6.2
2.0
8.0
2.0
10.5
tPHZ
Output Disable Time
1.0
5.5
(Note 11)
(Note 11)
ns
tPZL
1.0
5.5
Symbol
Parameter
TA 40qC to 85qCTA 40qC to 85qC
Units
VCC 4.5V–5.5V
VCC 4.5V–5.5V
CL 50 pF
CL 250 pF
8 Outputs Switching
8 Outputs Switching
(Note 12)
(Note 13)
Max
Max
tOSHL (Note 14)
Pin to Pin Skew, HL Transitions
1.0
1.5
ns
tOSLH (Note 14)
Pin to Pin Skew, LH Transitions
1.0
1.5
ns
tPS (Note 16)
Duty Cycle, LH–HL Skew
1.4
3.5
ns
tOST (Note 14)
Pin to Pin Skew, LH/HL Transitions
1.5
3.9
ns
tPV (Note 15)
Device to Device Skew, LH/HL Transitions
2.0
4.0
ns
Symbol
Parameter
Typ
Units
Conditions
(TA 25qC)
CIN
Input Capacitance
5
pF
VCC 0V
COUT (Note 17)
Output Capacitance
9
pF
VCC 5.0V


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