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2

Unit Loading/Fan Out

Mode Select-Function Table

H

= HIGH Voltage Level steady state

h

= HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition

L

= LOW Voltage Level steady state

I

= LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition

X

= Immaterial

 = LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

MR

Master Reset (Active LOW)

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

Data Outputs

50/33.3

−1 mA/20 mA

Operating Mode

Inputs

Output

MR

CP

Reset (Clear)

L

X

X

L

Load “1”

H



hH

Load “0”

H



lL