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74F323PC Datenblatt(PDF) 2 Page - Fairchild Semiconductor |
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74F323PC Datenblatt(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a paral- lel load operation. Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA DS0 Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA DS7 Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA S0, S1 Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA SR Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE1, OE2 3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Multiplexed Parallel Data Inputs 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Q0, Q7 Serial Outputs 50/33.3 −1 mA/20 mA Inputs Response SR S1 S0 CP LX X Synchronous Reset; Q0–Q7 = LOW HHH Parallel Load; I/On → Qn HL H Shift Right; DS0 → Q0, Q0 → Q1, etc. HH L Shift Left; DS7 → Q7, Q7 → Q6, etc. H L L X Hold |
Ähnliche Teilenummer - 74F323PC |
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Ähnliche Beschreibung - 74F323PC |
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