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2

Unit Loading/Fan Out

Functional Description

The 74F544 contains two sets of eight D-type latches, with

separate input and output controls for each set. For data

flow from A to B, for example, the A-to-B Enable (CEAB)

Table. With CEAB LOW, a LOW signal on the A-to-B Latch

Enable (LEAB) input makes the A-to-B latches transparent;

a subsequent LOW-to-HIGH transition of the LEAB signal

puts the A latches in the storage mode and their outputs no

longer change with the A inputs. With CEAB and OEAB

both LOW, the 3-STATE B output buffers are active and

reflect the data present at the output of the A latches. Con-

trol of data flow from B to A is similar, but using the CEBA,

LEBA and OEBA inputs.

Data I/O Control Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Note: A-to-B data flow shown; B-to-A flow control is the same, except using

CEBA, LEBA and OEBA

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

OEAB

A-to-B Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

OEBA

B-to-A Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

CEAB

A-to-B Enable Input (Active LOW)

1.0/2.0

20

µA/−1.2 mA

CEBA

B-to-A Enable Input (Active LOW)

1.0/2.0

20

µA/−1.2 mA

LEAB

A-to-B Latch Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

LEBA

B-to-A Latch Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

A-to-B Data Inputs or

3.5/1.083

70

µA/−650 µA

B-to-A 3-STATE Outputs

150/40(33.3)

−3 mA/24 mA (20 mA)

B-to-A Data Inputs or

3.5/1.083

70

µA/−650 µA

A-to-B 3-STATE Outputs

600/106.6(80)

−12 mA/64 mA (48 mA)

Inputs

Latch

Status

Output

Buffers

CEAB

LEAB

OEAB

H

X

X

Latched

High Z

X

H

X

Latched

—

L

L

X

Transparent

—

X

X

H

—

High Z

L

X

L

—

Driving