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ACE25C200 Datenblatt(PDF) 4 Page - ACE Technology Co., LTD. |
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ACE25C200 Datenblatt(HTML) 4 Page - ACE Technology Co., LTD. |
4 / 32 page ACE25C200 2MB Serial Flash Memory VER 1.2 4 Pin descriptions Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. Serial Data Input, Output and I/Os (DI, DO and DQ0, DQ1): The ACE25C200 supports standard SPI and Dual SPI operation. Standard SPI instructions use the unidirectional D I (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual SPI instructions use the bidirectional DQ pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ0, DQ1) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When CS# is brought low, the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. The CS# input must track the VCC supply level at power -up (see “9 Write Protection” and Figure 23). If needed a pull-up resister on CS# can be used to accomplish this. HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same SPI signals. The HOLD# pin is active low. Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The WP# pin is active low. Memory Organization The ACE25C200 array is organized into 1,024 programmable pages of 256-bytes each. Up to 256 bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The ACE25C200 has 64 erasable sectors and 4 erasable 64-k byte blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. |
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