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DM74LS240SJ Datenblatt(PDF) 1 Page - Fairchild Semiconductor

Teilenummer DM74LS240SJ
Bauteilbeschribung  Octal 3-STATE Buffer/Line Driver/Line Receiver
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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© 2000 Fairchild Semiconductor Corporation
DS006411
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS240 • DM74LS241
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring
400 mV of hysteresis at each low current PNP data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 133
Ω.
Features
s 3-STATE outputs drive bus lines directly
s PNP inputs reduce DC loading on bus lines
s Hysteresis at data inputs improves noise margins
s Typical IOL (sink current)
24 mA
s Typical IOH (source current)
−15 mA
s Typical propagation delay times
Inverting
10.5 ns
Noninverting
12 ns
s Typical enable/disable time 18 ns
s Typical power dissipation (enabled)
Inverting
130 mW
Noninverting
135 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74LS240
DM74LS241
Order Number
Package Number
Package Description
DM74LS240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS241WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS241N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide


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