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DM74LS299WM Datenblatt(PDF) 1 Page - Fairchild Semiconductor |
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DM74LS299WM Datenblatt(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS009827 www.fairchildsemi.com October 1988 Revised March 2000 DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description The DM74LS299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possi- ble: hold (store), shift left, shift right and load data. The par- allel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascad- ing. A separate active LOW Master Reset is used to reset the register. Features s Common I/O for reduced pin count s Four operation modes: shift left, shift right, load and store s Separate shift right serial input and shift left serial input for easy cascading s 3-STATE outputs for bus oriented applications Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol VCC = Pin 20 GND = Pin 10 Pin Descriptions Connection Diagram Order Number Package Number Package Description DM74LS299WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS299N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description CP Clock Pulse Input (Active Rising Edge) DS0 Serial Data Input for Right Shift DS7 Serial Data Input for Left Shift S0, S1 Mode Select Inputs MR Asynchronous Master Reset Input (Active LOW) OE1, OE2 3-STATE Output Enable Inputs (Active LOW) I/O0–I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs Q0–Q7 Serial Outputs |
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Ähnliche Beschreibung - DM74LS299WM |
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