© 2000 Fairchild Semiconductor Corporation

DS006483

www.fairchildsemi.com

August 1986

Revised May 2000

DM74S280

9-Bit Parity Generator/Checker

General Description

These universal, nine-bit parity generators/checkers utilize

Schottky-clamped TTL high-performance circuitry, and fea-

ture odd/even outputs to facilitate operation of either odd or

even parity applications. The word-length capability is eas-

ily expanded by cascading.

The DM74S280 can be used to upgrade the performance

of most systems utilizing the DM74180 parity generator/

checker. Although the DM74S280 is implemented without

expander inputs, the corresponding function is provided by

the availability of all input at pin 4, and no internal connec-

tion at pin 3. This permits the DM74S280 to be substituted

for the 180 in existing designs to produce an identical func-

tion, even if DM74S280’s are mixed with existing 180’s.

Input buffers are provided so that each input represents

only one normal 74S load, and full fan-out to 10 normal

Series 74S loads is available from each of the outputs at

low logic levels. A fan-out to 20 normal Series 74S loads is

provided at high logic levels, to facilitate connection of

unused inputs to used inputs.

Features

s Generates either odd or even parity for nine data lines

s Cascadable for N-bits

s Can be used to upgrade existing systems using MSI par-

ity circuits

s Typical data-to-output delay—14 ns

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Order Number

Package Number

Package Description

DM74S280M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74S280N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Number of Inputs

Outputs

(A Thru I) that are HIGH

∑ Even

∑ Odd

0, 2, 4, 6, 8

H

L

1, 3, 5, 7, 9

L

H