© 2000 Fairchild Semiconductor Corporation

DS006453

www.fairchildsemi.com

August 1986

Revised April 2000

DM74S40

Dual 4-Input NAND Buffer

General Description

This device contains two independent gates each of which

performs the logic NAND function.

Ordering Code:

Connection Diagram

Function Table

Y

= ABCD

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Either LOW or HIGH Logic Level

Order Number

Package Number

Package Description

DM74S40N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Output

AB

CD

Y

XXX

L

H

XX

L

X

H

XL

X

X

H

L

XXX

H

HH

HH

L