AD9683BCPZRL7-170 datasheet(4/44 Pages) AD

Teilenummer	AD9683BCPZRL7-170

Bauteilbeschribung	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

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Hersteller	AD [Analog Devices]

Direct Link	http://www.analog.com

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4 / 44 page

AD9683

Data Sheet

Rev. 0 | Page 4 of 44

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p

full-scale input range, duty cycle stabilizer enabled, default SPI, unless otherwise noted.

Table 1.

AD9683-170

AD9683-250

Parameter

Temperature

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±9

mV

Gain Error

Full

−6.6/−0.3

−5.3/+1.2

%FSR

Differential Nonlinearity (DNL)

Full

±0.8

±0.75

LSB

25°C

±0.5

LSB

Integral Nonlinearity (INL)1

Full

±1.6

±2.7

LSB

25°C

±0.8

±1.5

LSB

TEMPERATURE DRIFT

Offset Error

Full

±7

ppm/°C

Gain Error

Full

±13

±39

ppm/°C

INPUT REFERRED NOISE

VREF = 1.75 V

25°C

1.38

1.42

LSB rms

ANALOG INPUT

Input Span

Full

1.75

V p-p

Input Capacitance2

Full

2.5

pF

Input Resistance3

Full

20

kΩ

Input Common-Mode Voltage

Full

0.9

V

POWER SUPPLIES

Supply Voltage

AVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

DVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

Supply Current

IAVDD

Full

135

151

149

163

mA

IDRVDD + IDVDD

Full

68

73

92

97

mA

POWER CONSUMPTION

Sine Wave Input

Full

365

403

434

468

mW

Standby Power4

Full

221

266

mW

Power-Down Power5

Full

9

mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and its complement.

3

Input resistance refers to the effective resistance between one differential input pin and its complement.

4

Standby power is measured with a low input frequency, full-scale sine wave, and the CLK± pins active. Address 0x08 is set to 0x20, and the PDWN pin is asserted.

5

Power-down power is measured with a low input frequency, a full-scale sine wave, RFCLK pulled high, and the CLK± pins active. Address 0x08 is set to 0x00, and the

PDWN pin is asserted.

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