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AD7787BRMZ Datenblatt(PDF) 11 Page - Analog Devices |
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AD7787BRMZ Datenblatt(HTML) 11 Page - Analog Devices |
11 / 20 page Data Sheet AD7787 Rev. A | Page 11 of 20 Table 6. Register Selection RS1 RS0 Register Register Size 0 0 Communications Register during a Write Operation 8-Bit 0 0 Status Register during a Read Operation 8-Bit 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register 24-Bit Table 7. Channel Selection CH1 CH0 Channel 0 0 AIN1(+) − AIN1(−) 0 1 AIN2 1 0 AIN1(−) − AIN1(−) 1 1 VDD Monitor STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY (1) ERR (0) 0 (0) 0 (0) 1 (1) 1 (1) CH1 (0) CH0 (0) Table 8. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write operation to start a conversion. SR5 to SR4 0 These bits are automatically cleared. SR3 to SR2 1 These bits are automatically set. SR1 to SR0 CH1 to CH0 These bits indicate which channel is being converted by the ADC. |
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