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KMC7448HX1700LD Datenblatt(PDF) 5 Page - Freescale Semiconductor, Inc |
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KMC7448HX1700LD Datenblatt(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 60 page MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4 Freescale Semiconductor 5 Features — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle • Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation programmable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle — Caches can be disabled in software. — Caches can be locked in software. — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — Parity support on cache — No snooping of instruction cache except for icbi instruction — Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. • Level 2 (L2) cache interface — On-chip, 1-Mbyte, eight-way set-associative unified instruction and data cache — Cache write-back or write-through operation programmable on a per-page or per-block basis — Parity support on cache tags — ECC or parity support on data — Error injection allows testing of error recovery software • Separate memory management units (MMUs) for instructions and data — 52-bit virtual address, 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set-associative and use an LRU replacement algorithm. – TLBs are hardware- or software-reloadable (that is, a page table search is performed in hardware or by system software on a TLB miss). |
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