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CDCM7005RGZTG4 Datenblatt(PDF) 5 Page - Texas Instruments |
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CDCM7005RGZTG4 Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 45 page CDCM7005 www.ti.com SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013 Table 1. PIN ASSINGMENT (continued) TERMINAL I/O DESCRIPTION NAME BGA QFN LVCMOS reference clock selection input. In the manual mode the REF_SEL signal selects one of the two input clocks: REF_SEL A2 35 I REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected; The input has an internal 150-k Ω pullup resistor. CP_OUT A4 31 O Charge pump output Bias voltage output to be used to bias unused complementary input VCXO_IN for VBB C1 40 O single ended signals. The output of VBB is VCC – 1.3 V. The output current is limited to about 1.5 mA. This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting. STATUS_REF or In case of STATUS_REF, the LVCMOS output provides the Status of the C8 23 O PRI_SEC_CLK Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high. In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected. This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting. In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO STATUS_VCXO D8 22 O input (frequencies above 2 MHz are interpreted as valid clock; active high). or I_REF_CP In case of I_REF_CP, it provides the current path for the external reference resistor (12 k Ω ±1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 k Ω is selected (default setting), this pin can be left open. LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see feature description). This output can be programmed to be digital lock detect or analog lock detect (see feature description). The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect window for a predetermined number of successive clock cycles. PLL_LOCK A8 25 I/O The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect window or if a certain frequency offset between reference frequency and feedback frequency (VCXO) is detected. Both, the lock detect window and the number of successive clock cycles are user definable (via SPI). Y0A:Y0B F1, G1, 46, 47, The outputs of the CDCM7005 are user definable and can be any combination of Y1A:Y1B H2, H3, 3, 4, up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are Y2A:Y2B H4, H5, 7, 8, O selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are Y3A:Y3B H6, H7, 11,12, LVPECL. Y4A:Y4B G8, F8 16, 17 Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :CDCM7005 |
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