HCPL-7710 datasheet(8/17 Pages) AVAGO

Teilenummer	HCPL-7710

Bauteilbeschribung	40 ns Propagation Delay, CMOS Optocoupler 8 ns maximum pulse width distortion

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Hersteller	AVAGO [AVAGO TECHNOLOGIES LIMITED]

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8

Notes:

1. The LED is ON when VI is low and OFF when VI is high.

2. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.

tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.

3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaranteed. Maximum Data Rate is

the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent

jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is

30%, the maximum data rate becomes 37.5 MBd. Note: HCPL-x710 performances above 12.5 MBd are not guaranteed by Avago.

4. PWD is defined as |tPHL - tPLH|. %PWD(percent pulse width distortion) is equal to the PWD divided by pulse width.

5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within

the recommended operating conditions.

6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common

mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and

falling common mode voltage edges.

7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.

8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

9. In accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detec-

tion current limit, II-O ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detec-

tion current limit, II-O ≤ 5 µA).

10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled

“Optocoupler Input-Output Endurance Voltage.”

11. CI is the capacitance measured at pin 2 (VI).

0

VI (V)

5

4

HCPL-0710 fig 1

1

4

12

3

5

3

2

0 °C

25 °C

85 °C

4.5

1.6

VDD1 (V)

5.5

2.1

HCPL-0710 fig 2

1.7

5.25

4.75

5

2.2

2.0

1.8

1.9

0 °C

25 °C

85 °C

0

15

TA (C)

80

27

HCPL-0710 fig 3

17

60

20 30

29

25

19

21

10

40 50

70

23

TPLH

TPHL

Figure 1. Typical output voltage vs. input voltage

Figure 2. Typical input voltage switching threshold vs.

input supply voltage

Figure 3. Typical propagation delays vs. temperature

Package Characteristics

Parameter

Symbol Min.

Typ.

Max.

Units

Test Conditions

Input-Output Momentary

Withstand Voltage [8, 9, 10]

0710

VISO

3750

Vrms

RH = 50%,

t = 1 min.,

TA = 25 °C

7710

3750

Option 020

5000

Resistance

(Input-Output) [8]

RI-O

1012

Ω

VI-O = 500 Vdc

Capacitance

(Input-Output) [8]

CI-O

0.6

pF

f = 1 MHz

Input Capacitance [11]

CI

3.0

Input IC Junction-to-Case

Thermal Resistance

-7710

qjci

145

°C/W

Thermocouple

located at center

underside of package

-0710

160

Output IC Junction-to-Case

Thermal Resistance

-7710

qjco

140

-0710

135

Package Power Dissipation

PPD

150

mW

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