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FM25C640UE Datenblatt(PDF) 8 Page - Fairchild Semiconductor

Teilenummer FM25C640UE
Bauteilbeschribung  64K-Bit SPI??Interface Serial CMOS EEPROM
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FM25C640UE Datenblatt(HTML) 8 Page - Fairchild Semiconductor

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FM25C640U Rev. B
Bit0 (/RDY) indicates the Busy/Ready status of the EEPROM.
This bit is a read-only bit and is read by executing RDSR
instruction. If this bit is “1” then the EEPROM is busy doing a
program cycle. If this bit is “0” then the EEPROM is ready.
Note that if a RDSR instruction is executed when an internal
programming cycle is in progress, only the /RDY bit is valid.
All other bits are don’t cares.
The RDSR command requires the following sequence. The /CS
pin is pulled low to select the EEPROM and then the RDSR
opcode is transmitted on the SI pin. After this is done, data on the
SI pin becomes don’t care. The data from the Status Register is
then shifted out on the SO pin starting with D7 bit first and D0 last.
See
Figure 6.
FIGURE 6. Read Status Register
WRITE SEQUENCE (WRITE):
Write to the array is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
Also, the address of the memory location(s) to be programmed
must be outside the protected address field selected by the Block
Write Protection Level. See Table 4.
TABLE 4. Block Write Protection Levels
Level
Status Register Bits
Array
Address
BP1
BP0
Protected
0
0
0
None
1
0
1
1800-1FFF
2
1
0
1000-1FFF
3
1
1
0000-1FFF
A WRITE command requires the following sequence. The /CS pin
is pulled llow to select the EEPROM, then the WRITE opcode is
transmitted on the SI pin followed by two bytes of address, "High
byte addr" (A15-A8) and "Low byte addr" (A7-A0), further followed
by the data (D7-D0) to be written. See Figure 9. Note that only A12-
A0 address bits are treated valid by FM25C640U while bits A15-
A13 are ignored.
FIGURE 9. Byte Write
/CS
SI
SO
RDSR
OP-CODE
RDSR DATA
WRITE ENABLE (WREN):
When V
CC is applied to the EEPROM, it “powers up” in a write-
disabled state. Therefore, all programming modes (Write to memory
array and Status register), must be preceded by a WRITE EN-
ABLE (WREN) instruction. See
Figure 7.
FIGURE 7. Write Enable
/CS
SI
SO
WREN Op-Code
WRITE DISABLE (WRDI):
Executing this instruction disables all programming modes (Write
to memory array and Status register), preventing the EEPROM
from accidental writes.
Once WRDI instruction is executed,
WREN instruction should be executed to re-enable all program-
ming modes. See
Figure 8.
FIGURE 8. Write Disable
/CS
SI
SO
WRDI Op-Code
;;;;
CS
SI
SO
Write
Opcode
High Addr
Byte
Low Addr
Byte
Data
High Z
Internally, the programming will start after the /CS pin is brought
back to a high level. Note that the LOW to HIGH transition of the
/CS pin must occur during the SCK low time immediately after
clocking in the D0 data bit. See
Figure 10.
FIGURE 10. Start of Programming
SCK
SI
SO
/CS
D0
D1
D2
High Z
Start of internal
programming
Programming status (Busy/Ready) of the EEPROM can be deter-
mined by executing a READ STATUS REGISTER (RDSR) in-
struction after a write command. Upon executing the RDSR
instruction, if Bit 0 of the RDSR data is “1”, it indicates the WRITE
cycle is still in progress. If it is “0” then the WRITE cycle has ended.
Note that while the internal programming is still in progress (Bit 0
= 1), only the RDSR instruction is enabled. It is recommended that
no other instruction be issued till the internal programming is
complete.


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