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FM93C56 Rev. C.1

The Erase all instruction will program all locations to a logical “1”

state. Input information (Start bit, Opcode and Address) for this

WDS instruction should be issued as listed under Table1. After

inputting the last bit of data (A0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. Refer

Erase

All cycle diagram.

Note: The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL”

instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The

“ERASE” and “ERASE ALL” instructions are included to maintain compatibility with

earlier technology EEPROMs.Clearing of Ready/Busy status

When programming is in progress, the Data-Out pin will display

the programming status as either BUSY (low) or READY (high)

when CS is brought high (DO output will be tri-stated when CS is

low). To restate, during programming, the CS pin may be brought

high and low any number of times to view the programming status

without affecting the programming operation. Once programming

is completed (Output in READY state), the output is ‘cleared’

(returned to normal tri-state condition) by clocking in a Start Bit.

After the Start Bit is clocked in, the output will return to a tri-stated

condition. When clocked in, this Start Bit can be the first bit in a

command string, or CS can be brought low again to reset all

internal circuits. Refer

Clearing Ready Status diagram.

Related Document

Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-

PROM.