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AD9959BCPZ Datenblatt(PDF) 3 Page - Analog Devices |
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AD9959BCPZ Datenblatt(HTML) 3 Page - Analog Devices |
3 / 44 page AD9959 Rev. B | Page 3 of 44 GENERAL DESCRIPTION The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of fre- quency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation. The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/ SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation. The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to all channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier. The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9959 operates over the industrial temperature range of −40°C to +85°C. Σ DAC Σ DAC Σ DAC DAC TIMING AND CONTROL LOGIC 32 AD9959 32 10 15 CH0_IOUT 10 cos(x) DDS CORE CH0_IOUT 32 32 10 15 CH1_IOUT 10 cos(x) DDS CORE CH1_IOUT 32 32 10 15 CH2_IOUT 10 cos(x) DDS CORE CH2_IOUT 32 DFTW FTW SYNC_CLK CLK_MODE_SEL BUFFER/ XTAL OSCILLATOR SYSTEM CLK 1.8V AVDD DVDD SYNC_IN SYNC_OUT I/O_UPDATE 32 32 PHASE/ ΔPHASE AMP/ ΔAMP 10 14 10 15 CH3_IOUT 10 DDS CORE CH3_IOUT DAC_RSET REF_CLK REF_CLK PWR_DWN_CTL MASTER_RESET SCLK SDIO_0 SDIO_1 SDIO_2 SDIO_3 CS SCALABLE DAC REF CURRENT MUX SERIAL I/O PORT BUFFER CONTROL REGISTERS CHANNEL REGISTERS PROFILE REGISTERS ÷4 REF CLOCK MULTIPLIER 4× TO 20× 1.8V P0 P1 P2 P3 DVDD_I/O cos(x) ΣΣ Σ Σ Σ Σ Σ Σ Σ Figure 2. Detailed Block Diagram |
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