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FM25W256-G Datenblatt(PDF) 8 Page - Cypress Semiconductor |
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FM25W256-G Datenblatt(HTML) 8 Page - Cypress Semiconductor |
8 / 14 page FM25W256 - 256Kb SPI F-RAM Document Number: 001-84506 Rev. ** Page 8 of 14 CS SCK SI SO 0 1 2 3 4 5 6 7 0 0 Hi-Z 1 MSB LSB 0 1 2 3 4 6 7 X 0 Op-code 16-bit Address 0 0 1 11 12 13 14 0 1 2 3 4 5 6 7 7 Data In 0 1 2 3 4 5 6 MSB LSB 7 0 0 0 0 Figure 9. Memory Write (WREN must precede WRITE) CS SCK SI SO 0 1 2 3 4 5 6 7 0 0 Hi-Z 1 MSB LSB 0 1 2 3 4 6 7 X 0 Op-code 16-bit Address 0 1 11 12 13 14 0 1 2 3 4 5 6 7 7 Data Out 0 1 2 3 4 5 6 MSB LSB 7 0 1 0 0 0 Figure 10. Memory Read Endurance The FM25W256 device is capable of operating at least 10 14 read or write cycles. A F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A14-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 4K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 20MHz clock rate. Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop SCK Freq (MHz) Endurance Cycles/sec. Endurance Cycles/year Years to Reach 10 14 Cycles 20 37,310 1.18 x 10 12 85.1 10 18,660 5.88 x 10 11 170.2 5 9,330 2.94 x 10 11 340.3 |
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Ähnliche Beschreibung - FM25W256-G |
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