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Am79C940BJI Datenblatt(PDF) 1 Page - Rochester Electronics |
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1 / 13 page 79C940 © 2013 Rochester Electronics, LLC. All Rights Reserved 03112013 Specification Number 79C940B-CI (A) Rev C Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA Modular architecture allows easy tuning to specific applications High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs Direct FIFO read/write access for simple interface to DMA controllers or l/O processors Arbitrary byte alignment and little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADI) for external hardware address filtering in bridge/router applications JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI) Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port Sleep mode allows reduced power consump- tion for critical battery powered applications 5 MHz-25 MHz system clock speed Support for operation in industrial temperature range (–40°C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA Modular architecture allows easy tuning to specific applications High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs Direct FIFO read/write access for simple interface to DMA controllers or l/O processors Arbitrary byte alignment and little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADI) for external hardware address filtering in bridge/router applications JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI) Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port Sleep mode allows reduced power consump- tion for critical battery powered applications 5 MHz-25 MHz system clock speed Support for operation in industrial temperature range (–40°C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein. For complete Rochester ordering guide, please refer to page 3 Please consult factory for specific package availability |
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