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Si4735-D60-GM Datenblatt(PDF) 9 Page - Silicon Laboratories

Teilenummer Si4735-D60-GM
Bauteilbeschribung  BROADCAST AM/FM/SW/LW RADIO RECEIVER
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Hersteller  SILABS [Silicon Laboratories]
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Si4735-D60-GM Datenblatt(HTML) 9 Page - Silicon Laboratories

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Si4730/31/34/35-D60
Rev. 1.1
9
Table 4. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0—
400
kHz
SCLK Low Time
tLOW
1.3
µs
SCLK High Time
tHIGH
0.6
µs
SCLK Input to SDIO
Setup
(START)
tSU:STA
0.6
µs
SCLK Input to SDIO
Hold
(START)
tHD:STA
0.6
µs
SDIO Input to SCLK
Setup
tSU:DAT
100
ns
SDIO Input to SCLK
Hold4,5
tHD:DAT
0—
900
ns
SCLK input to SDIO
Setup
(STOP)
tSU:STO
0.6
µs
STOP to START Time
tBUF
1.3
µs
SDIO Output Fall Time
tf:OUT
—250
ns
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
—300
ns
SCLK, SDIO Capacitive Loading
Cb
——
50
pF
Input Filter Pulse Suppression
tSP
50
ns
Notes:
1.
When VD = 0 V, SCLK and SDIO are low impedance.
2.
When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3.
When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4.
The Si473x-D60 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5.
The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
20 0.1
Cb
1pF
-----------
+
20 0.1
Cb
1pF
-----------
+


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