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AD5272BRMZ-100-RL7 Datenblatt(PDF) 10 Page - Analog Devices

Teilenummer AD5272BRMZ-100-RL7
Bauteilbeschribung  1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rheostat
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5272BRMZ-100-RL7 Datenblatt(HTML) 10 Page - Analog Devices

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AD5272/AD5274
Data Sheet
Rev. D | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
VSS
2
A
3
W
4
10
9
8
SCL
ADDR
7
5
EXT_CAP
SDA
6
GND
AD5272/
AD5274
TOP VIEW
(Not to Scale)
RESET
Figure 4. MSOP Pin Configuration
ADDR
VDD 1
VSS
2
A
3
W
4
RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6 GND
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
AD5272/
AD5274
(EXPOSED
PAD)
Figure 5. LFCSP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
2
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3
W
Wiper terminal of RDAC. VSS ≤ VW ≤ VDD.
4
VSS
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
5
EXT_CAP
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6
GND
Ground Pin, Logic Ground Reference.
7
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.
10
ADDR
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).
EPAD
Exposed Pad
(LFCSP Only)
Leave floating or tie to VSS.


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