Data Sheet

AD7904/AD7914/AD7924

Rev. C | Page 9 of 32

TIMING SPECIFICATIONS

Table 4.

Parameter1

Description

Unit

10

10

kHz min

20

20

MHz max

50

50

ns min

Minimum quiet time required between the CS rising edge and the start

of the next conversion

10

10

ns min

CS to SCLK setup time

t33

35

30

ns max

Delay from CS until DOUT three-state disabled

t4 3

40

40

ns max

Data access time after SCLK falling edge

ns min

SCLK low pulse width

ns min

SCLK high pulse width

10

10

ns min

SCLK to DOUT valid hold time

t84

15/45

15/35

ns min/ns max

SCLK falling edge to DOUT high impedance

10

10

ns min

DIN setup time prior to SCLK falling edge

5

5

ns min

DIN hold time after SCLK falling edge

20

20

ns min

16th SCLK falling edge to CS high

1

1

μs max

Power-up time from full shutdown/auto shutdown modes

1

The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2

Mark/space ratio for the SCLK input is 40/60 to 60/40.

3

4

time of the part and is independent of the bus loading.

1.6V

200µA

200µA

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Digital Output Timing Specifications