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AD5121BCPZ100-RL7 Datenblatt(PDF) 10 Page - Analog Devices |
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AD5121BCPZ100-RL7 Datenblatt(HTML) 10 Page - Analog Devices |
10 / 32 page AD5121/AD5141 Data Sheet Rev. 0 | Page 10 of 32 Parameter1 Test Conditions/Comments Min Typ Max Unit Description t 12 Standard mode 300 ns Fall time of SCL signal, t FCL Fast mode 20 + 0.1 C L 300 ns t SP 3 Fast mode 0 50 ns Pulse width of suppressed spike (not shown in Figure 3) 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. Table 6. Control Pins Parameter Min Typ Max Unit Description t 1 1 µs End command to LRDAC falling edge t 2 50 ns Minimum LRDAC low time t 3 0.1 10 µs RESET low time tEEPROM_PROGRAM1 15 50 ms Memory program time (not shown in Figure 6) tEEPROM_READBACK 7 30 µs Memory readback time (not shown in Figure 6) t POWER_UP 2 75 µs Power-on EEPROM restore time (not shown in Figure 6) t RESET 30 µs Reset EEPROM restore time (not shown in Figure 6) 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after V DD − VSS is equal to 2.3 V. SHIFT REGISTER AND TIMING DIAGRAMS DATA BITS DB8 DB15 (MSB) DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS BITS A0 A1 A2 C2 C1 C0 A3 C3 CONTROL BITS DB7 Figure 2. Input Shift Register Contents t7 t6 t2 t4 t11 t12 t6 t5 t10 t1 SCL SDA P S S P t3 t8 t9 Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence) C3 t4 t2 t3 t5 t6 C2 C1 C0 D7 D6 D5 D2 D1 D0 SDI *PREVIOUS COMMAND RECEIVED. SCLK SYNC C3* SDO C2* C1* C0* D7* D6* D5* D2* D1* D0* t8 t9 t10 t7 t1 Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 |
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