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ADMP621ACEZ-RL Datenblatt(PDF) 10 Page - Analog Devices

Teilenummer ADMP621ACEZ-RL
Bauteilbeschribung  Wide Dynamic Range Microphone with PDM Digital Output
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ADMP621
Data Sheet
When long wires are used to connect the codec to the ADMP621,
a source termination resistor can be used on the clock output of
the codec instead of a buffer to minimize signal overshoot or
ringing. Match the value of this resistor to the characteristic
impedance of the CLK trace on the PCB. Depending on the
drive capability of the codec clock output, a buffer may still be
needed, as shown in Figure 17.
SLEEP MODE
The microphone enters sleep mode when the clock frequency falls
below 1 kHz. In this mode, the microphone data output is in a
high impedance state. The current consumption in sleep mode
is less than 5.5 µA.
The ADMP621 enters sleep mode within 1 ms of the clock
frequency falling below 1 kHz. The microphone wakes up
from sleep mode and begins to output data 32,768 cycles after the
clock becomes active. For a 3.072 MHz clock, the microphone
starts to output data in 10.7 ms. For a 2.4 MHz clock, the
microphone starts to output data in 13.7 ms. The wake-up
time, as specified in Table 2, indicates the time from when the
clock is enabled to when the ADMP621 outputs data within 3 dB
of its settled sensitivity.
START-UP TIME
The start-up time of the ADMP621 from when the clock is
active is the same as the wake-up time. The microphone starts up
32,768 cycles after the clock is active.
Rev. 0 | Page 10 of 16


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