Datenblatt-Suchmaschine für elektronische Bauteile |
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AD650SD Datenblatt(PDF) 9 Page - Analog Devices |
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AD650SD Datenblatt(HTML) 9 Page - Analog Devices |
9 / 20 page Data Sheet AD650 Rev. E | Page 9 of 20 If the approximate amount of noise that appears on CINT is known (VNOISE), then the value of CINT can be checked using the following inequality: NOISE S OS INT V V A t C V 3 10 1 3 (8) For example, consider an application calling for a maximum frequency of 75 kHz, a 0 V to 1 V signal range, and supply voltages of only ±9 V. The component selection guide of Figure 9 is used to select 2.0 kΩ for RIN and 1000 pF for COS. This results in a one-shot time period of approximately 7 μs. Substituting 75 kHz into Equation 7 yields a value of 1300 pF for CINT. When the input signal is near zero, 1 mA flows through the integration capacitor to the switched current sink during the reset phase, causing the voltage across CINT to increase by approximately 5.5 V. Because the integrator output stage requires approximately 3 V headroom for proper operation, only 0.5 V margin remains for integrating extraneous noise on the signal line. A negative noise pulse at this time could saturate the integrator, causing an error in signal integration. Increasing CINT to 1500 pF or 2000 pF provides much more noise margin, thereby eliminating this potential trouble spot. 1MHz 100kHz 10kHz 50 100 1000 COS (pF) INPUT RESISTOR 16.9k 20k 40.2k 100k Figure 9. Full-Scale Frequency vs. COS 100 20 50 100 1000 ONE SHOT CAPACITOR COS (pF) 1000 INPUT RESISTOR 16.9k 40.2k 100k 20k Figure 10. Typical Nonlinearity vs. COS |
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Ähnliche Beschreibung - AD650SD |
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