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DAC3484 Datenblatt(PDF) 7 Page - Texas Instruments

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Teilenummer DAC3484
Bauteilbeschribung  Wideband Transmit-Receive Digital Signal Processors
Download  49 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

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40 LVDS (1.8V)
40 LVDS (1.8V)
TX
Format
and
DAC
Interface
Control and Sync CMOS (3.3 V)
JTAG CMOS (3.3 V)
2
2
8
4
16
uP addr
24 LVDS (1.8V)
(1.8V)
1–4 TX Streams
Up to 8 DACs
(2 40-Pin Ports)
GC5330, GC5337
TESTMOD,
RESET
uP data
60 LVDS (1.8V)
60 LVDS (1.8V)
Up to 8 ADCs
(2 30-Pin Ports)
1 ADC
(1 16-Pin Port)
High-
Speed
Sync,
Clocks
16 CMOS (3.3V)
2 LVDS
2 LVDS
DPD clk
4 LVDS
Sync A, B in
Capture Buffer A
Capture Buffer B
Sync out
24 LVDS
ADC
inter-
face
(port
AB)
ADC
inter-
face
(port C)
uP ctrl
INT
B0445-01
SPI en,
SPI clk
SPIDIO
LVDS
showing
the number
of pins;
each signal
is a diff pair
SPIDO
(SPARE)
Mux
and
Sum
(TX)
or
Dist
(RX)
Baseband
Interface
Power
Meter,
per
Channel
beAGC
per
Channel
TX
Complex
Gain per
Channel
FIR
1 ,
2
´
´
Farrow
1024
1–
´
1–12 Channel DDUC Block
(config as TX or RX, showing TX)
CIC
1–3´
X
NCO
DPD
and
TX
Eq
UC
1/2´
CFR
TX
1–2 Streams
Includes
interp
before or
after CFR,
80% BW,
90 dB stop
1/2/3/4
80% BW,
90 dB stop;
90% BW,
80 dB stop
´
40% BW,
90 dB stop
ET
BUC
Eq
(16
Taps)
BDC
RX 1/2/4 Streams
1/2/4/8/16´
I/Q
Imbal
Correction
When I/Q correction
enabled, IF NCO is disabled
Interval Based Power Meter
IF
NCO
Switch
R2C
fe-
AGC
DC
Offset
Cancel
DVGA
Format/
GPIO
Running Avg Power Meter
TX
IF
Mux
and
Sum
IF NCO
X
4
JTAG
GC5330
GC5337
www.ti.com
SLWS226 B
– DECEMBER 2010 – REVISED JANUARY 2011
NOTE: UC1 and UC2 are for CFR interpolation; UC2 can only be used if UC1 is also used.
Figure 6. GC533x Block Diagram
GC533x Introduction
The GC533x is a flexible transmit and receive digital signal processor that includes receiver and transmitter
blocks, digital downconverter / upconverter (DDUC) blocks, crest factor reduction (CFR) and digital predistortion
(DPD) engines, flexible LVDS data converter and baseband interfaces, and capture buffers for DPD and adaptive
filtering algorithms.
Each of the four DDUC blocks can be configured as either a digital downconverter (DDC) or a digital upconverter
(DUC). Typically, a system can be implemented as both TX and RX, with both DDC and DUC functions. The
DDUC blocks provide programmable FIR filters with flexible numbers of taps, depending on signal bandwidth and
number of channels, as well as fractional resamplers, CIC filters, and complex mixers. The DDUC complex
mixers support static or hopping tuning functions.
beAGC after the DDC is part of the baseband interface. Static gain is applied in the BB block for both the DDC
output and DUC input.
The receiver block provides dc offset correction, front-end AGC, real-to-complex conversion, complex mixing,
decimating filters, a complex equalizer, and a blind RX IQ imbalance correction function.
The CFR block reduces the peak-to-average ratio (PAR) of complex, arbitrary TX signals. Reducing the PAR of
the TX signal allows wireless-infrastructure (WI) base stations and repeaters to use smaller and lower-cost
multi-carrier power amplifiers (MCPAs).
The DPD block can process one or two TX streams at 62 MHz {74 MHz} or four TX streams at 31 MHz {37 MHz}
each, with fifth-order nonlinear correction. The DPD engine uses a companion TI DSP TMS320C6748 to collect
the reference and feedback data, calculate the feedforward correction, and update the GC533x registers.
© 2010–2011, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): GC5330 GC5337


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