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ADR03 Datenblatt(PDF) 5 Page - Analog Devices

Teilenummer ADR03
Bauteilbeschribung  12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface
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Direct Link  http://www.analog.com
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ADR03 Datenblatt(HTML) 5 Page - Analog Devices

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Data Sheet
AD5444/AD5446
Rev. E | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VDD = 4.5 V to
5.5 V
VDD = 2.5 V to
5.5 V
Unit
Conditions/Comments
fSCLK
50
50
MHz max
Maximum clock frequency.
t1
20
20
ns min
SCLK cycle time.
t2
8
8
ns min
SCLK high time.
t3
8
8
ns min
SCLK low time.
t4
8
8
ns min
SYNC falling edge to SCLK active edge setup time.
t5
5
5
ns min
Data setup time.
t6
4.5
4.5
ns min
Data hold time.
t7
5
5
ns min
SYNC rising edge to SCLK active edge setup time
t8
30
30
ns min
Minimum SYNC high time.
t9
23
30
ns min
SCLK active edge to SDO valid.
Update Rate
2.7
2.7
MSPS
Consists of cycle time, SYNC high time, data setup time and output
voltage settling time.
1 Guaranteed by design and characterization; not subject to production test.
t7
t1
t3
t2
t4
t5
t6
DB15
DB0
SCLK
SYNC
SDIN
t8
Figure 2. Standalone Timing Diagram
DB15 (N)
DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
SCLK
SDIN
SDO
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
t4
t5
t6
t2
t1
t3
t7
t8
t9
DB15 (N)
DB0 (N)
SYNC
Figure 3. Daisy-Chain Timing Diagram


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