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CDCVF2510A Datenblatt(PDF) 4 Page - Texas Instruments

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Teilenummer CDCVF2510A
Bauteilbeschribung  3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
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ABSOLUTE MAXIMUM RATINGS
CDCVF2510A
SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 ............................................................................................................................................... www.ti.com
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDCVF2510A clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK
24
I
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBIN
13
I
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
G
11
I
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
FBOUT
12
O
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-
Ω series-damping resistor.
3, 4, 5, 8, 9,
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
1Y (0:9)
15, 16, 17, 20,
O
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
21
Each output has an integrated 25-
Ω series-damping resistor.
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
AVCC
23
Power
can be used to bypass the PLL. When AVCC is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
AGND
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 14, 22
Power
Power supply
GND
6, 7, 18, 19
Ground Ground
over operating free-air temperature range (unless otherwise noted)
AVCC
Supply voltage range (1)
AVCC < VCC + 0.7 V
VCC
Supply voltage range
-0.5 V to 4.3 V
VI
Input voltage range (2)
-0.5 V to 4.6 V
VO
Voltage range applied to any output in the high or low state (2)(3)
–0.5 V to VCC + 0.5 V
IIK
Input clamp current, (VI < 0)
–50 mA
IOK
Output clamp current, (VO < 0 or VO > VCC)
±50 mA
IO
Continuous output current, (VO = 0 to VCC)
±50 mA
Continuous current through each VCC or GND
±100 mA
ZθJA
Junction-to-ambient package thermal impedance (4)
114.5°C/W
ZθJC
Junction-to-case thermal impedance (4)
25.7°C/W
TJ
Maximum allowable junction temperature
125°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
AVCC must not exceed VCC + 0.7 V.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This value is limited to 4.6 V maximum.
(4)
The package thermal impedance and junction-to-case thermal impedance are calculated in accordance with JESD51 (no air flow
condition) and JEDEC252P (high-k board).
4
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