Datenblatt-Suchmaschine für elektronische Bauteile |
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TSB81BA3E Datenblatt(PDF) 11 Page - Texas Instruments |
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TSB81BA3E Datenblatt(HTML) 11 Page - Texas Instruments |
11 / 57 page TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL PFP ZAJ DESCRIPTION PACKAGE PACKAGE NAME TYPE NO. NO. I/O PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 mF and 0.001 mF. Lower frequency 10-mF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-CORE, PLLVDD- Supply 31 N7 – DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device 3.3 to provide noise isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection. Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in RESET CMOS 75 A6 I the Applications Information section). The RESET terminal also incorporates an internal pulldown, which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain-type driver. This terminal must normally be left unconnected. When this terminal is probed, the terminal shows a 98.304-MHz signal. If this is perceived as an RSVD Osc Out 26 M5 O EMI problem, then the terminal may be pulled to ground through a 10-k Ω resistor. However, this causes an increase of up to 340 mA in device current consumption. Current setting resistor terminals. These terminals are connected to a R0 23 N3 precision external resistance to set the internal operating currents and cable Bias – R1 22 N2 driver output currents. A resistance of 6.34 k Ω, ±1%, is required to meet the IEEE Std 1394-1995 output voltage limits. Test control input. This input is used in the manufacturing test of the SE CMOS 35 M10 I TSB81BA3E. For normal use this terminal must be pulled low either through a 1-k Ω resistor to GND or directly to GND. Test control input. This input is used in the manufacturing test of the SM CMOS 36 N10 I TSB81BA3E. For normal use this terminal must be pulled low either through a 1-k Ω resistor to GND or directly to GND. Test control input. This input is used in the manufacturing test of the TESTM CMOS 78 A3 I TSB81BA3E. For normal use this terminal must be pulled high through a 1-k Ω resistor to VDD. Voltage regulator power-down input. When asserted logic high, this pin will power-down the internal 3.3-V to 1.95-V regulator. For single 3.3-V supply VREG_PD CMOS 73 B7 I operation, this pin should be tied to GND. If an external regulator is used to supply the 1.95-V PLLVDD-CORE and DVDD-CORE power rails this terminals should be pulled to Vcc through a 1-k Ω resistor to VDD. Port-0 twisted-pair differential-signal terminals. Board traces from each pair TPA0– 45 K13 of positive and negative differential signal terminals must be kept matched TPA0+ 46 J13 Cable I/O and as short as possible to the external load resistors and to the cable TPB0– 41 M13 connector. Request the S800 1394b layout recommendations document TPB0+ 42 L13 from your Texas Instruments representative. Port-1 twisted-pair differential-signal terminals. Board traces from each pair TPA1– 52 F13 of positive and negative differential signal terminals must be kept matched TPA1+ 53 E13 Cable I/O and as short as possible to the external load resistors and to the cable TPB1– 48 H13 connector. Request the S800 1394b layout recommendations document TPB1+ 49 G13 from your Texas Instruments representative. Port-2 twisted-pair differential-signal terminals. Board traces from each pair TPA2– 58 B13 of positive and negative differential signal terminals must be kept matched TPA2+ 59 A13 Cable I/O and as short as possible to the external load resistors and to the cable TPB2– 55 D13 connector. Request the S800 1394b layout recommendations document TPB2+ 56 C13 from your Texas Instruments representative. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TSB81BA3E |
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