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AD7918BRUZ-REEL7 Datenblatt(PDF) 9 Page - Analog Devices |
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AD7918BRUZ-REEL7 Datenblatt(HTML) 9 Page - Analog Devices |
9 / 32 page AD7908/AD7918/AD7928 Rev. D | Page 9 of 32 TIMING SPECIFICATIONS AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.1 Table 4. Limit at TMIN, TMAX AD7908/AD7918/AD7928 Parameter AVDD = 3 V AVDD = 5 V Unit Description fSCLK2 10 10 kHz min 20 20 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next conversion t2 10 10 ns min CS to SCLK setup time t33 35 30 ns max Delay from CS until DOUT three-state disabled t43 40 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to DOUT valid hold time t84 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance t9 10 10 ns min DIN setup time prior to SCLK falling edge t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min 16th SCLK falling edge to CS high t12 1 1 μs max Power-up time from full power-down/auto shutdown mode 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. TO OUTPUT PIN 50pF IOH IOL CL 200µA 200µA 1.6V Figure 2. Load Circuit for Digital Output Timing Specifications |
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