LM27403

SNVS896 A – AUGUST 2013 – REVISED SEPTEMBER 2013

www.ti.com

DESCRIPTION (CONTINUED)

The LM27403 has a conventional voltage-mode control loop with high gain-bandwidth error amplifier and PWM

input voltage feedforward to simplify compensation design and enable excellent transient response throughout

the full line voltage and load current ranges. Forced-PWM (FPWM) operation eliminates frequency variation to

minimize EMI in sensitive applications. An open-drain Power Good circuit provides power-rail sequencing and

fault reporting. Other features include programmable system-level thermal shutdown with automatic recovery,

output voltage remote sense, configurable soft-start, monotonic startup into prebiased loads, an integrated bias

supply low-dropout (LDO) regulator, external power supply tracking, precision enable with customizable

hysteresis for programmable line undervoltage lockout (UVLO), and synchronization capability for beat frequency

sensitive and multiregulator applications. The LM27403 is offered in a 4-mm x 4-mm thermally-enhanced WQFN-

24 package with 0.5-mm pitch.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

–0.3

22

V

VDD, PGOOD

–0.3

6

V

SS/TRACK, SYNC, FADJ, COMP, FB, RS

–0.3

V

UVLO/EN

–0.3

V

–0.3

24

V

CBOOT to SW

–0.3

6

V

CS+ to CS–

–1

1

V

OTP, D+, D–

–0.3

V

–65

150

°C

Thermal

–40

150

°C

Electrostatic discharge

Human body model (HBM) QSS 009-105 (JESSD22-A114A)

2

kV

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other condition beyond those included under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

(2)

All voltages are with respect to the network ground terminal unless otherwise noted.

(3)

The SW pin can tolerate negative voltage spikes as low as –10 V and as high as 30 V for a duration up to 10 ns.

(4)

Body diode of the low-side MOSFET notwithstanding, parasitic inductance in a real application may result in the SW voltage ringing

negative.

(5)

The CBOOT pin can tolerate positive voltage spikes as high as 35 V for a duration up to 10 ns.

(6)

The human body model (HBM) is a 100-pF capacitor discharged through a 1.5-k

Ω resistor to each pin.

2

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: LM27403