Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC102S021CIMM Datenblatt(PDF) 6 Page - Texas Instruments |
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ADC102S021CIMM Datenblatt(HTML) 6 Page - Texas Instruments |
6 / 25 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Track Hold Power Up Track Hold b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 9 10 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DIN DOUT Power Up SCLK CS Power Down Control register Control register DB9 DB8 DB9 DB8 ADC102S021 SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com ADC102S021 Timing Specifications (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Parameter Test Conditions Typ Limits(1) Units VA = +3.0V +4 tEN Delay from CS Until DOUT active 30 ns (max) VA = +5.0V +2 VA = +3.0V +16.5 tACC Data Access Time after SCLK Falling Edge 30 ns (max) VA = +5.0V +15 tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) VA = +3.0V 1.7 Output Falling VA = +5.0V 1.2 tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max) VA = +3.0V 1.0 Output Rising VA = +5.0V 1.0 Timing Diagrams Figure 3. ADC102S021 Operational Timing Diagram Figure 4. Timing Test Circuit 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC102S021 |
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