CDCVF25081

3.3-V PHASED-LOCK LOOP CLOCK DRIVER

SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003

2

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NAME

PIN NO.

TYPE

DESCRIPTION

1Y[0:3]

2, 3, 14, 15

O

Bank 1Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated

25-

Ω series-damping resistor.

2Y[0:3]

6, 7, 10, 11

O

Bank 2Yn clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated

25-

Ω series-damping resistor.

CLKIN

1

I

Clock input. CLKIN provides the clock signal to be distributed by the CDCVF25081 clock driver. CLKIN is

used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must

have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and

a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to

CLKIN.

FBIN

16

I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the

outputs to complete the feedback loop of the internal PLL. The integrated PLL synchronizes the FBIN and

output signal so there is nominally zero-delay from input clock to output clock.

GND

5, 12

Ground

Ground

S1, S2

9, 8

I

Select pins to determine mode of operation. See the FUNCTION TABLE for mode selection options.

VDD

4, 13

Power

Supply voltage. The supply voltage range is 3 V to 3.6 V