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AD845JR-16-REEL7 Datenblatt(PDF) 8 Page - Analog Devices

Teilenummer AD845JR-16-REEL7
Bauteilbeschribung  Precision, 16 MHz CBFET Op Amp
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AD845JR-16-REEL7 Datenblatt(HTML) 8 Page - Analog Devices

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AD845
REV. E
–8–
Figure 5. Settling Time of the 3-Op Amp Instrumentation
Amplifier. Horizontal Scale is 200 ns/Div, Vertical Scale,
Positive Pulse Input is 5 V/Div and Output Settling is
1 mV/Div.
Figure 6. Settling Time of the Three Op Amp Instru-
mentation Amplifier. Horizontal Scale: 200 ns/Div; Vertical
Scale, Negative Pulse Input: 5 V/ Div; Output Settling:
1 mV/Div.
DRIVING THE ANALOG INPUT OF AN A/D CONVERTER
An op amp driving the analog input of an A/D converter, such
as that shown in Figure 7, must be capable of maintaining a
constant output voltage under dynamically changing load condi-
tions. In successive approximation converters, the input current
is compared to a series of switched trial currents. The compari-
son point is diode clamped but may deviate several hundred
millivolts, resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open-loop value. Most IC amplifiers exhibit a minimum
open-loop output impedance of 25
W due to current limiting
resistors. A few hundred microamps reflected from the change
in converter loading can introduce errors in instantaneous input
voltage. If the A/D conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier’s output
will return to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth, yielding slow recovery from output transients. The
AD845 is ideally suited to drive high resolution A/D converters
with 5
ms or longer conversion times since it offers both wide
bandwidth and high open-loop gain.
Figure 7. AD845 As ADC Unity Gain Buffer


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