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AD5290YRMZ10 Datenblatt(PDF) 4 Page - Analog Devices |
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AD5290YRMZ10 Datenblatt(HTML) 4 Page - Analog Devices |
4 / 20 page AD5290 Data Sheet Rev. C | Page 4 of 20 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth −3 dB BW Code = 0x80 470 kHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.006 % VW Settling Time tS VA = 10 V, VB = 0 V, ±1 LSB error band 4 µs Resistor Noise Voltage eN_WB RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz 1 Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 All parts have a 35 ppm/°C temperature coefficient. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic-level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = +15 V and VSS = −15 V. |
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Ähnliche Beschreibung - AD5290YRMZ10 |
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