Datenblatt-Suchmaschine für elektronische Bauteile |
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AD7801BR Datenblatt(PDF) 9 Page - Analog Devices |
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AD7801BR Datenblatt(HTML) 9 Page - Analog Devices |
9 / 16 page AD7801 –9– REV. 0 VOUT = 2 ×V REF N 256 where: N is the decimal equivalent of the binary input code. N ranges from 0 to 255. VREF is the voltage applied to the external REFIN pin when the external reference is selected and is VDD/2 if the internal reference is used. Table I. Output Voltage for Selected Input Codes Digital Analog Output MSB . . . LSB 1111 1111 2 × 255 256 ×V REF V 1111 1110 2 × 254 256 ×V REF V 1000 0001 2 × 129 256 ×V REF V 1000 0000 V REF V 0111 1111 2 × 127 256 ×V REF V 0000 0001 2 × V REF 256 V 0000 0000 0 V 2VREF VREF 0 DAC INPUT CODE 00 01 7F 80 81 FE FF Figure 26. DAC Transfer Function POWER-ON RESET The AD7801 has a power-on reset circuit designed to allow output stability during power up. This circuit holds the DAC in a reset state until a write takes place to the DAC. In the reset state all zeros are latched into the input register of the DAC and the DAC register is in transparent mode thus the output of the DAC is held at ground potential until a write takes place to the DAC. The power-on reset circuitry generates a PON STRB signal which is a gating signal used within the logic to identify a power-on condition. POWER-DOWN FEATURES The AD7801 has a power-down feature implemented by exercising the external PD pin. An active low signal puts the complete DAC into power-down mode. When in power-down, the current consumption of the device is reduced to less than 1 µA max at +25°C or 2 µA max over temperature, making the device suitable for use in portable battery powered equipment. The internal reference resistors, the reference bias servo loop, the output amplifier and associated linear circuitry are all shut down when the power-down is activated. The output terminal sees a load of ≈ 23 kΩ to GND when in power-down mode as shown in Figure 25. The contents of the data register are unaffected when in power-down mode. The device typically comes out of power-down in 13 µs (see Figure 10). VDD 11.7k Ω 11.7k Ω IDAC VREF Figure 25. Output Stage During Power-Down Analog Outputs The AD7801 contains a voltage output DAC with 8-bit resolution and rail-to-rail operation. The output buffer provides a gain of two at the output. Figures 2, 3 and 4 show the source and sink capabilities of the output amplifier. The slew rate of the output amplifier is typically 7.5 V/ µs and has a full-scale settling to eight bits with a 100 pF capacitive load in typically 1.2 µs. The input coding to the DAC is straight binary. Table I shows the binary transfer function for the AD7801. Figure 26 shows the DAC transfer function for binary coding. Any DAC output voltage can be expressed as: |
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