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AD7817ARU Datenblatt(PDF) 6 Page - Analog Devices |
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AD7817ARU Datenblatt(HTML) 6 Page - Analog Devices |
6 / 20 page AD7817/AD7818 Data Sheet Rev. D | Page 6 of 20 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Sample tested during initial release and after any redesign or process changes that may affect the parameters. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 17, Figure 18, Figure 21, and Figure 22. Table 2. Parameter A Version/B Version Unit Test Conditions/Comments t POWER-UP 2 µs max Power-up time from rising edge of CONVST t 1a 9 µs max Conversion time Channel 1 to Channel 4 t 1b 27 µs max Conversion time temperature sensor t 2 20 ns min CONVST pulse width t 3 50 ns max CONVST falling edge to BUSY rising edge t 4 0 ns min CS falling edge to RD/WR falling edge setup time t 5 0 ns min RD/WR falling edge to SCLK falling edge setup t 6 10 ns min D IN setup time before SCLK rising edge t 7 10 ns min D IN hold time after SCLK rising edge t 8 40 ns min SCLK low pulse width t 9 40 ns min SCLK high pulse width t 10 0 ns min CS falling edge to RD/WR rising edge setup time t 11 0 ns min RD/WR rising edge to SCLK falling edge setup time t 12 1 20 ns max D OUT access time after RD/WR rising edge t 13 1 20 ns max D OUT access time after SCLK falling edge t 14a 1, 2 30 ns max D OUT bus relinquish time after falling edge of RD/WR t 14b 1, 2 30 ns max D OUT bus relinquish time after rising edge of CS t 15 150 ns max BUSY falling edge to OTI falling edge t 16 40 ns min RD/WR rising edge to OTI rising edge t 17 400 ns min SCLK rising edge to CONVST falling edge (acquisition time of T/H) 1 These figures are measured with the load circuit of Figure 3. They are defined as the time required for D OUT to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and 0.4 V or 2 V for VDD = 3 V ± 10%, as shown in Table 1. 2 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of the external bus loading capacitances. 200µA IOL 200µA IOL 1.6V TO OUTPUT PIN CL 50pF Figure 3. Load Circuit for Access Time and Bus Relinquish Time |
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Ähnliche Beschreibung - AD7817ARU |
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